This invention relates to wideband code division multiple access (WCDMA) for a communication system and more particularly to a simplified cell search scheme for WCDMA.
Present code division multiple access (CDMA) systems are characterized by simultaneous transmission of different data signals over a common channel by assigning each signal a unique code. This unique code is matched with a code of a selected receiver to determine the proper recipient of a data signal. These different data signals arrive at the receiver via multiple paths due to ground clutter and unpredictable signal reflection. Additive effects of these multiple data signals at the receiver may result in significant fading or variation in received signal strength. In general, this fading due to multiple data paths may be diminished by spreading the transmitted energy over a wide bandwidth. This wide bandwidth results in greatly reduced fading compared to narrow band transmission modes such as frequency division multiple access (FDMA) or time division multiple access (TDMA).
New standards are continually emerging for next generation wideband code division multiple access (WCDMA) communication systems as described in U.S. patent application Ser. No. 90/067,594, entitled Spread-Spectrum Telephony with Accelerated Code Acquisition, filed Apr. 27, 1998, and incorporated herein by reference. These WCDMA systems are coherent communications systems with pilot symbol assisted channel estimation schemes. These pilot symbols are transmitted as quadrature phase shift keyed (QPSK) known data in predetermined time frames to any receivers within the cell or within range. The frames may propagate in a discontinuous transmission (DTX) mode within the cell. For voice traffic, transmission of user data occurs when the user speaks, but no data symbol transmission occurs when the user is silent. Similarly for packet data, the user data may be transmitted only when packets are ready to be sent. The frames include pilot symbols as well as other control symbols such as transmit power control (TPC) symbols and rate information (RI) symbols. These control symbols include multiple bits otherwise known as chips to distinguish them from data bits. The chip transmission time (Tc), therefore, is equal to the symbol time rate (T) divided by the number of chips in the symbol (N). This number of chips in the symbol is the spreading factor.
A WCDMA mobile communication system must initially acquire a signal from a remote base station to establish communications within a cell. This initial acquisition, however, is complicated by the presence of multiple unrelated signals from the base station that are intended for other mobile systems within the cell as well as signals from other base stations. Moreover, normal signals from each base station are modulated by a common scrambling code or long code that distinguishes it from adjacent base stations. The duration of these long codes would normally inhibit rapid signal acquisition. The base station, therefore, continually transmits a special signal at 16 KSPS on a perch channel, much like a beacon, to facilitate this initial acquisition. The perch channel format includes a frame with sixteen time slots, each having a duration of 0.625 milliseconds. Each time slot includes four common pilot symbols, four transport channel data symbols and two search code symbols. These search code symbols include a first search code (FSC) symbol and a second search code (SSC) symbol transmitted in parallel. These search code symbols are not modulated by the long code, so a mobile receiver need not examine each of 512 long codes for the duration of each code to acquire a signal. Rather, spreading modulation of the search code symbols of the perch channel is limited to a 256 chip Gold sequence.
Referring to FIG. 3A, there is a simplified block diagram of a transmitter of the prior art for transmitting first and second search codes. Circuits 302 and 310 each produce a 256 cycle Hadamard sequence. Both sequences are modulated by a complement of a 64-cycle Gold sequence and three 64-cycle Gold sequences, thereby producing a 256-chip FSC symbol in parallel with a 256-chip SSC symbol. The block diagram of FIG. 3B illustrates a circuit of the prior art for detecting the FSC symbol of FIG. 3A. The circuit receives the FSC symbol as an input signal on lead 311. The signal is periodically sampled in response to a clock signal by serial register 321. The circuit has 64 taps that are multiplied with respective pseudo-noise (PN) signals to produce 64 output signals. Adder 348 adds these 64 output signals and produces a sequence of output signals at terminal 350. These output signals are loaded into serial register 391. Signal samples from register taps 350-376 produce sample outputs that adder 386 sums to produce a match signal MAT at lead 388. A coincidence of each chip of the received FSC symbol with the Gold PN sequence at zero time shift (FIG. 3C) results in a high correlation of all 256 chips. Any shift in the received chips of the FSC symbol with respect to the Gold PN sequence, however, results in a severely degraded correlation having a maximum peak of 70 chips. Thus, the high correlation indicates a match or acquisition of the FSC symbol from a base station.
Several problems with the circuit of FIG. 3B render this solution less than ideal. First, the 64-chip accumulator requires 64 taps and 64 logic gates. Second, the logic gates produce 64 output signals that must be combined by a 64-input adder at the chip rate multiplied by the oversampling rate. Finally, these circuit elements require extensive Layout area and increase power consumption. Both latter considerations are especially disadvantageous for mobile communications systems.
These problems are resolved by a first serial circuit coupled to receive an input signal in response to a clock signal. The first serial circuit has N taps arranged to produce a respective plurality of first tap signals from the input signal. A first logic circuit is coupled to receive the plurality of first tap signals and one of N predetermined signals and the complement of N predetermined signals. The first logic circuit produces a first output signal in response to the clock signal, the plurality of first tap signals and the one of N predetermined signals and the complement of N predetermined signals. A second serial circuit coupled to receive the first output signal. The second serial circuit has M taps arranged to produce a respective plurality of second tap signals from the first output signal, wherein a ratio of N/M is no greater than four. A second logic circuit is coupled to receive one of a true and a complement of each of the plurality of second tap signals. The second logic circuit produces a second output signal in response to the one of a true and a complement of each of the plurality of second tap signals.
The present invention provides synchronization capability that is comparable to circuits of the prior art. Circuit complexity including gate count and signal taps as well as power consumption are greatly reduced.